1. Field
Embodiments of the invention relate generally to a nonvolatile semiconductor memory device and a method for manufacturing the same.
2. Background Art
Conventionally, semiconductor memory devices, such as flash memories and the like have been formed by memory cells two-dimensionally integrated on the surfaces of silicon substrates. To decrease the bit unit cost of such semiconductor memory devices to make their capacities large, memory cells must be highly integrated. Recently, however, the high integration has been difficult in terms of costs and techniques.
As a technique to break through the limit of the high integration, there is a method to integrate three-dimensionally by stacking memory cells. However, simply stacking and processing one layer after another increase the process number as the stacked layer number increases, and the cost increases. Here is proposed a technique of stacking gate electrodes and an insulation film alternately to form a stacked body, collectively processing to form through-holes in the stacked body, stacking a block insulation film, a charge storage film and a tunnel insulation film in this order on the side surfaces of the though-holes, and burying silicon pillars inside the through-holes (for example, refer to JP-A 2007-266143 (Kokai)).
In such correctively processed three-dimensional stacked memory, memory cell transistors are formed at the intersections between each gate electrode and silicon pillars, and the potential of each gate electrode and each silicon pillar are controlled to input and output charges from the silicon pillar into the charge storage film, and information can be stored. This technique, in which the stacked body is correctively processed to form the through-holes, does not increase the number of the lithography process even when the stacking number of the gate electrode is increased, and the cost increase can be suppressed.
However, in such correctively processed three-dimensional stacked memory, it is difficult to form memory cell transistors of uniform characteristics all over the stacked body. For example, in forming the through-holes in the stacked body, it is extremely difficult to process the side surfaces of the through-holes perfectly vertical, and taper angles are formed especially at the portions where the through-holes pierce the insulation films. Accordingly, the through-holes in the lower part of the stacked body are thinner in comparison with the upper part thereof. This varies the characteristics of the memory transistors.